What is Computer BUS?
A computer system is made up of 3 major components. Central Processing Unit (CPU) that processes data, Memory Unit that holds data for processing and the Input and Output Unit that is used by the user to communicate with the computer. But how do these different components of a CPU communicate with each other?
They use a special electronic communication system called the BUS. Just like a passenger bus that carries people, the computer bus carries lots of information using numerous pathway called circuit lines. In this article, we are going to discuss the single bus structure in computer organization.
Single bus structure in computer organization:
In single bus structure inside the CPU, different components are linked by a single bus. The various components available inside CPU in this architecture includes Instruction Register (IR), Instruction Decoder (ID), Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Arithmetic and Logic Unit (ALU) and General purpose Register. Now, the question is what are CPU registers and what are the types of registers used in single bus structure? Let’s discuss these in details.
What are CPU registers?
The CPU registers are the high-speed memory location built into the microprocessor. CPU uses these memory locations to store data and instructions temporarily for processing. That is why they are also called as the fastest temporary memory device. Since they are available inside the CPU, therefore CPU can access them quickly. CPU processes, stores and transfers data from one component to another with the help of registers.
Since we have different generations of computers and the efficiency, speed, accuracy etc are varies among the different generation of computers, so the number of registers and the size of the registers also varies among computers. Therefore it is true that the performance of a CPU also depends on registers. The main job of a register is to receive the information, holds it temporarily and pass it on, as directed by the Control Unit.
In single bus structure, the CPU uses Instruction Register (IR), Instruction Decoder (ID), Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR) and General purpose Register during processing to perform different operations. Let’s discuss all these registers along with ALU and how they work together in the single bus structure.
Instruction Register (IR):
Instruction Register holds the current instruction that is being executed. It doesn’t store any address but stores the instruction. If we require which instruction is currently being executed by the CPU, then we will look at the contents of IR which tells us the currently executing instruction.
Instruction Decoder (ID):
Program Counter (PC):
Program Counter keeps the tracks of instruction that is to be executed next to the competition of the current instruction. So the program counter is a type of register which doesn’t store any instruction but stores the address of next instruction to be executed. When the instruction is fetched, the value of PC is automatically incremented and it points to the address of next instruction.
Memory Address Register (MAR):
Memory Address Register holds the address of active memory location. When CPU wants to store or read data from memory, CPU stores the required address of memory location in MAR.
Memory Data Register (MDR):
Memory Data Register holds data. The primary job of MDR is to handle the data transfer between the main memory and the processor. That means it holds the contents of location read from or written in the memory.
Arithmetic & Logic Unit (ALU):
Arithmetic & Logic Unit is the component where actual execution is performed. ALU is one of the significant parts of the computer system which is capable of performing different calculations. Depending on the design of ALU it makes the CPU more powerful, efficient as well as faster.
General Purpose Register:
The General Purpose Registers are used for different purposes including holding of intermediate results.
Now to understand how the single bus structure in computer organisation works, let us consider an instruction ADD A, B which is in location M of memory.
The address M is first placed in MAR and a read signal is generated by CPU. The content of location M i.e. ADD A, B instruction is placed in MDR which is then placed to Instruction Register (IR). This instruction is decoded by the Instruction Decoder (ID) and required signal components are activated to perform the addition operation.
First Operand address A is placed in MAR and read signal is generated. The operand content 5 is fetched from memory and placed in MDR. This data 5 is sent to ALU by the single bus. Second operand address B is placed in MAR and read signal is generated. Operand data 2 is fetched and placed in MDR. This data, 2 is then sent to ALU by the single bus. Once two operands are available inside the ALU, arithmetic addition is performed due to the signals generated by the system. The result 7 is temporarily placed in the general purpose register R0.
It is then sent to MDR by the single bus. An address of memory where the result data should be stored is placed in MAR. Once, the result data and address are placed in MDR and MAR respectively, write signal is generated which fetches the result data from CPU to proper memory position.
The considered instruction ADD A, B is in 2-address instruction format. In this format, 2nd operand source is destination also. Hence, MAR will hold B and result data 7 is placed to location B of memory.