**Types of Flip Flops in Digital Electronics: **The basic 1-bit digital memory circuit is known as flip-flops. It can have only two states, either the state 1 or 0. A flip-flop is also known as bit stable multi-vibrator. Flip-flops can be constructed by using NAND and NOR gates. The general block diagram represents a flip-flop that has one or more inputs and two outputs.

The two outputs are complementary to each other.

- If Q is 1 that is set Q’ to 0.
- If Q is 0, reset Q’ to 1. (Q and Q’ can’t be at the same state simultaneously. If it happens, it will violate the definition of the flip-flop and hence is called undefined condition).
- Q is called the state of the flip-flop whereas Q’ is called complementary state of the flip-flop.
- When the output Q is either 0 or 1, it remains in that state unless one or more inputs are excited to effect the change on the output.

## Types of Flip Flops in Digital Electronics:

The different types of Flip Flops are based on how their inputs and clock pulses cause the transition between 2 states. Basically, we have 4 different types of Flip Flops in digital electronics – SR, JK, D & T flip-flop. Let’s discuss all these 4 types of Flip Flops with their diagrams and truth tables.

## SR Flip-Flop (Set-Reset):

It has two inputs named Set and Reset and two outputs Q and Q’. The outputs are the complement to each other. The SR flip-flop can be implemented using NOR and NAND gates.

### SR Flip-Flop using NOR Gates:

SR flip-flop can be constructed with NOR gates by connecting NOR gates back to back. The crossed-coupled connection from gate 1 to the input of gate 2 constitute a feedback path. This circuit is not clocked. So, it is classified as the asynchronous sequential circuit.

### Block Diagram of SR Flip Flop Using NOR Gates:

### Truth Table of SR Flip-Flop using NOR Gates:

We have considered that the output of a NOR gate is 0 if any of the input is 1. The output is 1 only if all the inputs are 0.

### SR Flip-Flop using NAND Gates:

SR flip-flops can be constructed with NAND gates by connecting the NAND gates back to back and is represented as S’R’ flip-flop. The operation of S’R’ flip-flop can be analysed in a similar manner by employed the NAND gates based on SR flip-flop. This circuit is also not clocked.

### Block Diagram of SR Flip Flop Using NAND Gates:

### Truth Table of SR Flip Flops using NAND Gates:

A low at an input of a NAND gate forces the output to HIGH. The output of the NAND gate is 0 only if all the inputs of the NAND gate is 1.

## Clocked SR Flip Flop:

Generally, synchronize circuit changes their state only when clock pulses are present. We can modify the operation of the basic flip-flop by including an additional input to control the behaviour of the circuit. The circuit of SR flip-flop with clock consists of two AND gates. The clock input is connected to each of the AND gates, which results in LOW outputs when the clock input is LOW. In this situation, the changes in S and R input will not affect the state Q of the flip-flop. On the other hand, if the clock input is HIGH, the changes in S and R will be passed over by the AND gates and they will cause changes in the output Q of the flip-flop.

Any information either O or 1 can be stored in the flip-flop by applying a HIGH clock input. And by for any desired period of time by applying a LOW clock input. This type of flip-flop is called clocked SR flip-flop. Such a clocked SR flip-flop is shown below –

### Clocked SR Flip Flop Logic Diagram:

### Clocked SR Flip Flop Block Diagram:

### Characteristics table of SR flip-flop:

This table gives us an idea about the working of the flip-flop. We know that the next state flip-flop output (Q_{n+1}) depends on the present input as well as present output (Q_{n}). In order to know the next state output of a flip-flop, we have to consider the present state output also. The characteristic table of SR flip-flop is given below-

The expression for next output will be:

**Q _{n+1 }= (S + R’)Q_{n }**

Along with the above equation we have to consider the fact that S and R can’t be simultaneously low. So, in order to take this fact we have to consider another equation for SR flip-flop i.e:

**S.R = 0**

## D Flip-Flop:

This types of flip-flops have only one input referred to as D-input or data input and two outputs as Q and Q’. It transfers the data at the input point after the delay of one clock pulse at the output Q. So in some cases, the input is referred to as delay input and that is the reason why this types of flip-flops are called D flip-flop.

D flip-flop can be easily constructed from SR flip-flop by simply incorporating an inverter between S and R such that the input of the inverter is at the S end and output of the inverter is at the R end. The flip-flop is either used as a delay device on as a latch to store 1 bit of binary information. The structure of D flip-flop can be constructed using NAND gates as follows-

### Logic Diagram of D Flip-Flop:

### Truth Table of D Flip-Flop:

### Characteristic Table of D Flip-Flop:

We can construct the equation for D flip-flop from the characteristics equation of SR flip-flop. So, we can obtain:

**Q _{n+1 }= D**

**Q _{n+1 }= D + Q’**

## JK Flip-Flop:

A JK flip-flop has very similar characteristics to an SR flip-flop. The only difference is that the undefined condition for SR flip-flop i.e. S=R=1, this condition is also included in this case.

Inputs J and K behaves like inputs S and R to set and reset the flip-flop respectively. When J=k=1, the flip-flop is said to be in toggle state which means that the output switches to its complement state in every time a clock pulse. The data outputs are J and K which are ANDed with Q’ and Q respectively to obtain the inputs for S and R states.

### Block Diagram of JK Flip Flop:

It is always necessary to use the AND gates since the same function can be performed by adding an extra input terminal to each of the NAND gates 1 and 2 as shown below:

### Logic Diagram of JK Flip Flop:

### Truth Table of JK Flip Flop:

### Characteristic Table of JK Flip Flop:

## T flip-flop:

We can construct this types of Flip Flops easily with a slide modification of JK Flip Flop. If the two inputs J and K are tied together, it is referred to as a T Flip Flop. Hence T Flip Flop has only one input T and two outputs Q and Q’.

The name T Flip-Flop actually indicates that the Flip Flop has the ability to toggle state and memory state. Since there are two states, T Flip-Flop is a very good option to use in the counter design and in sequential circuit design where switching operations are required.

### Truth Table of T Flip Flop:

- If the T input is in 0 (Zero) state (J=K=0) the output Q will not change with the clock pulse.
- If the T input is in 1 (One) state (J=K=1) the output Q will change to Q’ with the clock pulse. In other words, we can say that if T is equal to 1, the device is clocked and the output toggles its state.

### Logic Diagram of T Flip Flop:

In this types of Flip Flops, when T=0 then Q_{n+1 }= Q_{n }i.e. the next state is same as present state and no change will occur. On the other hand, when T=1 then Q_{n+1 }= Q’_{n }i.e the next state of the Flip Flop is complemented to present state.

### Characteristic Table of T Flip Flop:

The characteristic equation of T flip-flop can be made as:

**Q _{n+1 }= TQ’_{n} + T’Q_{n}**

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**Also check:** **Logic Gates and Truth Table**

## SHARMYNE N CHEMHERE

23 May 2019THANK YOU, SIR, NOW ITS MUCH SIMPLER.