Types of Registers in Digital Electronics | Diagram-SISO,SIPO,PISO,PIPO Types of Registers in Digital Electronics: Registers in digital electronics are the group of binary storage cells capable of holding binary information. A  group of flip-flop constitutes a register since each flip-flop can work as a binary cell. An ‘n’ bit register has ‘n’ flip-flops and is capable of holding ‘n’ bit of information. In addition to flip-flop, a register can have a combinational part that performs data processing task. In this article, we will discuss all the various types of registers with their block diagram in details.

The above figure shows that one types of register constructed of 3 SR flip-flop with a common clock pulse input. The clock pulse enables all the flip-flop at the same instant of time so that the information available at the three inputs can be transferred into a 3-bit register. All the flip-flops in a register have to respond to the transition of the clock pulse. Latches are suitable to temporarily stored binary information that is to be transferred to an external destination. In the design of sequential circuits, they should not be used.

What is a Shift Register?

A shift register is capable of shifting its binary contents either to the left or to right. It basically permits the stored data to move from one particular location to some other location within the register. Registers can be designed using the different types of flip-flops available like SR, JK and D type. We can shift data in a shift register in two possible ways-

2. Parallel Shifting

The serial shifting method shifts one bit at a time for each clock pulse in a serial manner, beginning with either MSB (Most Significant Bit) or LSB (Least Significant Bit). On the other hand, in parallel shifting operation, all the data get shifted simultaneously during a single clock pulse. So, we can say that the parallel shifting operation is much faster than serial shifting method.

Types of Registers:

There are two ways to shift data into a register- serial & parallel. Also, two ways to shift the data out of the register. This leads to the construction of 4 basic types of registers –

1. Serial-in-Serial-out (SISO)
2. Serial-in-Parallel-out (SIPO)
3. Parallel-in-Serial-out (PISO)
4. Parallel-in-Parallel-out (PIPO) Serial-in-Serial-out Shift Register:

This types of registers accept data serially i.e. 1 bit at a time, at the single input line. The output is also obtained on a single output line in a serial manner. The data within the register may be shifted from left to right using shift left to register or may be shifted from right to left using shift right register.

Shift Right Register:

A shift right register can be constructed with either JK or D flip-flop. A JK flip-flop based shift register requires connection of both J and K inputs and they are connected to the leftmost flip-flop. To input a ‘0’, one should apply a ‘0’ at the J input that is J = 0 and K =1. With the application of a clock pulse, the data will be shifted by 1 bit to the right. In the shift right register using D flip-flop,  D input of the leftmost flip-flop is used as a serial input line. To input ‘0’, one should apply ‘0’ in the D input and vice versa. When the clock pulse applied, each flip-flop is either set or reset according to the data available at that point in time. Hence the input data bit at the serial line is inserted into flip-flop A by the first clock pulse. Also, the data of stage A is shifted into stage B at the same time and so on. For each clock pulse, the data stored in the register is shifted to the right by one stage.

Shift Left Register:

A shift left register can also be constructed with either JK or D flip-flop. The entry of the four-bit number 1110 into the register, beginning with the rightmost bit. A 0 is applied to serial input line making D is equal to 0. As the first clock pulse is applied, the flip-flop A is reset, thus storing the 0. Next, a 1 is applied to the serial input making D is equal to 1 for flip-flop A and D is equal to 0 for flip-flop B. This is because the input line of flip-flop B is connected to the output of A, QA. When the second clock pulse is applied, the 1 on the data input is shifted to the flip-flop A and the 0 in the flip-flop A is shifted to flip-flop B. The 1 in the binary number is now applied at the serial input line and the third clock pulse is applied. Now, 1 is entered in the flip-flop B and shifted to the next flip-flop that means 0 is the output of the flip-flop B and now applied to flip-flop C. Thus, the entry of the binary number in the shift right register is accomplished with the clock pulse A shifted to B and so on. Serial-in-parallel-out register (SIPO):

In this types of registers, the data is shifted in serially but shifted out parallelly. To obtain the output data in parallel, it is required that all the output bits are available at the same time. This can be obtained by connecting the output of each flip-flop to an output pin. The bits are available simultaneously, once the data is stored in the flip-flop.

In an 8-bit SIPO register, there are 8 SR flip-flops which are all sensitive to the negative clock transition. This register has two exceptions-

1. Each flip-flop has an asynchronous CLEAR input.
2. The true part of each flip-flop is available as an output. Thus, all 8 bits of any number stored in the register are available simultaneously as an output which is a parallel one. Parallel-in-Serial-out register (PISO):

In the previous two cases, the data are shifted in a serial manner that is a bit by bit. But in this types of registers, the data bits are entered into the flip-flops simultaneously rather than bit by bit manner.

In a 4-bit Parallel-in-Serial-out (PISO) register, there are 4 parallel data input lines A, B, C, D and SHIFT/LOAD (SH/LD) is a control input that allows the 4 bits of data to enter into the register in a parallel manner. When SH/LD is high AND gates G1, G3, and G5 are enabled, allowing the data bits to shift right from one stage to the next. If SH/LD is low, AND gates G2, G4, and G6 are enabled, allowing the data bits at the parallel inputs. When a clock pulse is applied, the flip-flop with D equal to 1 will be set and with D=0 will be reset. Therefore storing all the 4 bits simultaneously. The OR gates either allow the normal shifting operation or the parallel data entry operation, depending on which of the AND gates are enabled by SH/LD input. Parallel in Parallel out Register (PIPO):

These types of registers are designed such that data can be shifted into or out of the register in a parallel manner. The parallel input of data has no interconnection between the flip-flops since no serial shifting is required. Hence the moment of parallel entry of data is accomplished, the data will be available at the parallel outputs of the register.

In 4 bit of Parallel-in-Parallel-out types of registers, there are 4 parallel inputs to be applied at A, B, C, D. Inputs are directly connected to the input line of the respective D flip-flops. On applying the clock transition, these inputs are entered into the register and are immediately available at the outputs Q1, Q2, Q3, Q4. Universal Register:

A register which is capable of transferring data only in one direction is called a unidirectional shift register. On the other hand, the register which is capable of transferring data in both left and right direction is called a bidirectional shift register. If the register has both the shift left and shift right capabilities, along with the necessary input & output terminals for parallel transfer, then it is called a universal shift register.

The most general shift register can have the capabilities listed below –

•  A shift right control to enable the shift right operation and the serial input and output lines associated with the shift right register.
• A shift left control to enable the shift left operation and the serial input and output lines, associated with the shift left register.
• A parallel load control is to enable the parallel transfer and the ‘n’ input lines associated with the parallel transfer.
• A CLEAR control is to clear the register to 0.
• A clock (CLK) input for clock pulses to synchronize all the operations.
• A control state that leaves the information in the register unchanged even through clock pulses is continuously applied.

Functional table for universal register - 1. When S1 S2 = 0 0, the present value of the register is applied to the D input of the flip-flop. Hence this condition forms a path from the output of each flip-flop into the input of the same flip-flop. The next clock pulse transition transfers into each flip-flop that the binary value held previously. So no change of state occurs.
2. when S0 S1 = 0 1, terminals 1 of each register input have a path to the D input of each flip-flop. This occurs a shift right operation with the serial input transferred into the next flip-flop.
3. Similarly when S1 S0 = 1 0, a shift left operation results with the other serial input going into the previous flip-flop.
4. Finally, when S1 S0 = 1 1, the binary information on the parallel input lines is transferred into the register simultaneously during the next clock pulse.

So, a universal register is a general purpose register capable of performing three operations that is shift right, shift left and parallel load.

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Related: Types of Flip-Flops.